1. Field of the Invention
The present invention relates to a communication system which connects to a microprocessor for controlling an electric device with a peripheral device thereof.
2. Description of the Related Art
Recently, various kinds of electric devices, such as devices for controlling an engine, for controlling suspension, and for controlling an air conditioner are mounted on an automobile. For transmission control of a communication network between such electric devices mounted on an automobile, CSMA/CD (Carrier Sense Multiple Access/Collision Detection) method is often used on the ground of extensibility of a system, ease of transmission control, and so on (for example, CAN by Bosch, PALMNET by Mazda and so on).
Generally, a transmission control device of these data communication devices is made to be one-chip IC, in order to make it easy to mount various kinds of electric devices as abovementioned. Accordingly, in the following, the transmission control devices of these data communication device is referred to as a communication IC.
FIG. 1 is a block diagram showing the construction of a conventional communication IC disclosed, for example, in Japanese Patent Application Laid-Open No. 61-195453 (1986). In the construction of this conventional example, a dual port RAM (hereafter, to be called DPRAM) is used as a transmitting/receiving buffer memory.
In FIG. 1, reference numeral 100 designates the communication IC which is connected to a bus line (transmission line) 101. In the DPRAM 102, an IMP (Interface Management Processor) 103, which controls data transmitted to and from the bus line 101, is connected by a parallel bus inside of the communication IC 100, and a control microprocessor 200 is connected by an exterior parallel bus.
In the abovementioned connection of the control microcomputer 200 to the communication IC 100, a total of 19 signal lines, that is, eight data busses, and eight address busses, three control lines, are necessary in the case where it is assumed that an 8-bit microcomputer is used as a control microcomputer 200 and a memory space of the communication IC 100 is 256 bytes, and twelve signal lines are necessary even when a bus by multiplexing a data bus and an address bus is used.
Next, explanation will be given on the operation of the conventional communication IC disclosed in the abovementioned Japanese Patent Application Laid-Open No. 61-195453 (1986).
In FIG. 1, a data a string (hereinafter, to be called a frame) received from the bus line 101 is stored in the DPRAM 102 through a receiver branch 105, transmitter branch 106, a shift register 104 and the IMP 103. The control microcomputer 200 controls the communication IC 100 read/write operations in the same way as a usual RAM by connecting address signal lines, data signal lines, and control signal lines to the DPRAM 102 for access control. FIG. 2 is a flow chart in which communication control procedure of the control microcomputer 200 of the case where data transmission of the control microcomputer 200 and the communication IC 100 is carried out by using such DPRAM 102 as a abovementioned is shown.
At first, in step S00, it is determined whether or not there is a transmission request from the control microcomputer 200, and if not, the process of step S07 being a receiving process and the following steps will be carried out. In the case where there is a transmission request, accessing from the IMP 103 to the DPRAM 102 is prohibited in step S01, and a determination is made whether or not access is possible from the control microcomputer 200 to the DPRAM 102 in step S02. When accessing is impossible, the process is interrupted, and when it is possible, the process of writing transmission data to the DPRAM 102 is performed in step S03. Next, processing for setting transmission status is performed in step S04, and processing the transmission request in step S05, respectively, and thereafter, accessing the IMP 103 is allowed in step S06 to complete the transmission process.
In addition, receiving data from the bus line 101, whether or not there is a transmission request, is confirmed in step S07. If there is a request, access of the DPRAM 102 by the microcomputer 200 is judged in step S08, and if the accessing is impossible, processing is interrupted and receiving in the DPRAM 102 is read out in step S10 after the transmission request is temporarily cleared in step S09 after accessing becomes possible.
Since a conventional communication IC is connected to a control microcomputer by a parallel bus as abovementioned, a number input/output ports of a control microcomputer are necessary for signals required for connection. Therefore, it is necessary to increase the input/output ports of a control microcomputer.
A communication IC i82526 made by Intel Co. Ltd. avoids the abovementioned problem by setting up an increase port in a communication IC. However, the communication chip cannot be connected as a peripheral device for a miniaturized electronic device.
While, it is possible to carry out such a connection as abovementioned by using a synchronous or an asynchronous serial communication interface (UART, USRT, SPI and so on) integrated generally in a microcomputer, in the case where it is necessary to control operation states such as transmitting/receiving data and error management, it is too difficult to realize the connection only by transmission control protocol of an 8-bit unit whose procedure is not determined.